
`timescale 1 ns / 1 ps

	module mic_pdm2pcm_v1_0 #(
		parameter FOSR = 1,
		parameter FORD = 2
	)
	(
		// Users to add ports here
		input wire mic_bit_data,
		input wire[31:0] data_offset,
	//	input wire mic_clk,
	//	input wire mic_resetn,
		// User ports ends
		// Do not modify the ports beyond this line


		// Ports of Axi Master Bus Interface M_AXIS
		input wire  mo_axis_aclk,
		input wire  mo_axis_aresetn,
		output wire  mo_axis_tvalid,
		input wire  mo_axis_tready,
		output wire [31 : 0] mo_axis_tdata,
		output wire  mo_axis_tlast
	);
// Instantiation of Axi Bus Interface M_AXIS
	assign m_axis_tlast = 0;

	wire[31:0] 	t_data;
	wire 	   	t_valid;
	wire 	 	t_ready;

	assign mo_axis_tdata = t_data;
	assign mo_axis_tvalid = t_valid;
	assign t_ready = mo_axis_tready;

//	MIC_AXIS_CONVER u_MIC_AXIS_CONVER(
//		.s_axis_aresetn (mic_resetn ),
//		.s_axis_aclk    (mic_clk    ),
//		.s_axis_tvalid  (t_valid  ),
//		.s_axis_tready  (t_ready  ),
//		.s_axis_tdata   (t_data   ),
//
//		.m_axis_aclk    (mo_axis_aclk    ),
//		.m_axis_aresetn (mo_axis_aresetn ),
//		.m_axis_tvalid  (mo_axis_tvalid  ),
//		.m_axis_tready  (mo_axis_tready  ),
//		.m_axis_tdata   (mo_axis_tdata   )
//	);
	


	DATA_RES #(
		.F_FOSR(FOSR),
		.F_FORD(FORD)
	)u_DATA_RES(
		.clk        (mo_axis_aclk         	),
		.rst_n      (mo_axis_aresetn       ),
		.bit_data   (mic_bit_data    ),

		.r_data      (t_data      ),
		.r_ready     (t_ready     ),
		.rdata_valid (t_valid 	),
		.d_offset(data_offset)
	);
	

	// Add user logic here

	// User logic ends

	endmodule
